Lightly-doped drain (LDD) transistors have a lightly doped portion at both ends of the channel with heavily-doped portions spaced from the channel to form contacts. In the use of LDD transistors there has been discovered a problem created by hot carriers that result from high electric fields. Although attenuated in LDD transistors, hot carriers still cause a particular problem for the lightly-doped sources and drains of the LDD structure. Hot electrons get into the oxide above the lightly-doped regions and tend to deplete the mobile carriers from the surface of these lightly-doped regions. This causes an increase in the source and/or drain resistance which results in degradation in the gain of the transistor. This degradation is less if there are more mobile carriers which can be obtained by increasing the doping level of the lightly-doped source and drain. The increased doping level, however, also increases the internal electric field and the number of generated hot carriers, which thus increases the tendency of the hot carriers to drive the mobile carriers away from the surface of the lightly-doped regions. There has been determined an implant dosage of about 5.times.10.sup.13 of phosphorus for N channel transistors which has been found to be the optimum dosage for minimizing this problem. The problem, however, still exists even at that dosage. Additionally, the preferred dosage for other characteristics, such as gate-aided and avalanche breakdown, is less than that. Thus, the hot electrons and holes generated by internal electric fields reduce the useful lifetime of the transistor.
One solution was disclosed in an article, "A New LDD Transistor With Inverse T-Gate Structure," Tial-Yuan Huang et al, IEEE Electron Device Letters, Vol. EDL-8, No. 4, Apr. 1987. In that case the structure involved a T-shaped polysilicon gate which had a thick portion over the channel and a thin portion which was implanted through by the first implant to form the lightly-doped portion of the drain. Sidewall spacers were formed on the thick portion of the polysilicon gate for the mask for the second, heavy implant. This, however, resulted in close proximity of the gate to the heavily doped portion of the source/drain. There was then present excessive capacitance between the gate and the heavily doped source/drain regions. Such excessive capacitance is deleterious to circuit performance.